This invention relates to a method of manufacturing insulating-gate semiconductor device, more specifically to a method of manufacturing insulating-gate semiconductor device in which a fine trench structure is created based on trench width reduction using a self-aligned formation of an overlapping masking layer.
Recently, with the growth of the mobile computing/communication terminal market there has been an increasing demand for lithium-ion batteries which are smaller in size and yet larger in capacity. The protecting circuit board for the management of charging and discharging the lithium-ion battery has to be small in order to meet the need for total weight reduction of the mobile computing/communication terminal and in order to withstand short circuits due to excessive loads. In this application, it was required that the protecting circuit boards be small, as the boards were housed inside the container of the lithium-ion battery. This size reduction has been accomplished by the use of COB (Chip on Board) technology using multiple chip components. On the other hand, as the switching devices on the board such as power MOSFET are connected to the lithium-ion battery in series, there is also a need for reducing the on-state resistance of the switching devices. This is an indispensable ingredient in mobile telephone applications for extending the calling period and the stand-by period.
For achieving a low on-state resistance, developments have been made for increasing the cell density by applying micro-fabrication technology to the chip manufacturing process. As a result, in a typical planar structure where the channel was formed on the surface of the semiconductor substrate, the cell density was 7.4 million per square inch. Further, in the first-generation trench structure where the channel was formed along the side of the trench, the cell density was 25 million per square inch. Improvements were made in the second-generation trench structure so that the cell density reached 72 million per square inch.
As described above, the cell density has been increased by the adoption of the trench structure for forming the cells, and the on-state resistance has decreased accordingly. However, at this point, there is no room for manipulating the current micro-fabrication process for further reducing the size of the trench structure. The only way to achieve the reduction is to introduce a new exposure apparatus with a higher spatial resolution in the micro-fabrication process, if such an apparatus is available.
This invention involves a micro-fabrication process in which the process limitations due to the spatial resolution of the exposure apparatus used in the photolithographic process can be overcome by modifying the process for forming the masking layer for the trench, this overcomes the problems described above.
The invention provides method of manufacturing an insulating-gate semiconductor device that includes forming a channel layer on a drain region of a semiconductor substrate, forming an opening for forming a trench in a first insulating film formed on the surface of the semiconductor substrate, forming a side-wall film around a side wall of the opening for forming a trench by anisotropic etching of a second insulating film formed over the first insulating film, forming a trench piercing through the channel layer by etching using the first insulating film and the side-wall film as a mask, forming a gate insulating film on an inside wall of the trench, forming a gate electrode by filling the trench with a semiconductor material, and forming a source region adjacent to the trench in the surface region of the channel region.
In the manufacturing method described above, the side-wall film is formed based on a self-aligned formation of the second insulating film over the first insulating film. Thus, the side-wall film further reduces the width of the opening for forming a trench in the mask pattern, the processing limit of which is determined by the spatial resolution of the exposure apparatus used for creating the photoresist mask pattern. As a result, it is possible to create a trench structure of a size which is smaller than the spatial resolution of the exposure apparatus.
Based on this manufacturing method, it is possible to use current manufacturing facilities, especially the exposure apparatus, for manufacturing devices having finer trench structures than the current device without requiring advanced manufacturing facilities. For example, in a conventional process, the opening for forming a trench was 1.0 xcexcm, and accordingly the width of the trench was 1.0 xcexcm. When the manufacturing method of the invention was applied using the same manufacturing facilities, the opening for forming the trench was the same, but the width of the trench was reduced, by more than one half, to 0.4 xcexcm.
The manufacturing method of the invention increases the cell density by about two times while keeping the same operational surface area as the conventional device. Thus, the on-state resistance increases accordingly, and the properties of the switching device are improved.
Furthermore, it is another advantage of this invention that the smaller width of the trench allows the reduction of the cross-sectional area of the trench, resulting in a smaller capacitance between the gate and the source of the trench as well as a smaller capacitance between the gate and the drain of the trench. This type of capacitance has a significant influence on the cut-off frequency as input capacitance and feedback capacitance, the reduction of which improves the switching speed.